H8SLASH300H datasheet(74/552 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 May 15, 2007 Page 42 of 516

REJ09B0152-0300

3.1

Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than

one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1

Exception Sources and Vector Address

Source Origin

Exception Sources

Vector

Number

Vector Address

Priority

Reset pin/

watchdog timer

Reset

H'0000 to H'0001

High



Reserved for system use

1 to 6

H'0002 to H'000D

External interrupt

NMI

H'000E to H'000F

Trap instruction

TRAPA #0

Trap instruction #0

H'0010 to H'0011

Trap instruction

TRAPA #1

Trap instruction #1

H'0012 to H'0013

Trap instruction

TRAPA #2

Trap instruction #2

H'0014 to H'0015

Trap instruction

TRAPA #3

Trap instruction #3

H'0016 to H'0017



Reserved for system use

H'0018 to H'0019

CPU

Direct transition by executing the

SLEEP instruction

H'001A to H'001B



Reserved for system use

14, 15

H'001C to H'001F

External interrupts

IRQ0

H'0020 to H'0021

IRQ1

H'0022 to H'0023

IRQAEC

H'0024 to H'0025



Reserved for system use

19, 20

H'0026 to H'0029

Comparators

COMP0

H'002A to H'002B

COMP1

H'002C to H'002D

RTC

0.25-second overflow

H'002E to H'002F

0.5-second overflow

H'0030 to H'0031

Second periodic overflow

H'0032 to H'0033

Minute periodic overflow

H'0034 to H'0035

Hour periodic overflow

H'0036 to H'0037

Day-of-week periodic overflow

H'0038 to H'0039

Week periodic overflow

H'003A to H'003B

Free-running overflow

H'003C to H'003D

Low

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