H8SLASH300H datasheet(56/552 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 May 15, 2007 Page 24 of 516

REJ09B0152-0300

Table 2.8

System Control Instructions

Instruction

Size*

Function

TRAPA



Starts trap-instruction exception handling

RTE



Returns from an exception-handling routine.

SLEEP



Causes a transition to a power-down state.

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the CCR. The CCR size is one

byte, but in transfer from memory, data is read by word access.

STC

B/W

CCR

→ (EAd)

Transfers the CCR contents to a destination location. The condition

code register size is one byte, but in transfer to memory, data is written

by word access.

ANDC

CCR

∧ #IMM → CCR

Logically ANDs the CCR with immediate data.

ORC

CCR

∨ #IMM → CCR

Logically ORs the CCR with immediate data.

XORC

CCR

⊕ #IMM → CCR

Logically XORs the CCR with immediate data.

NOP



PC + 2

→ PC

Only increments the program counter.

Note:

Refers to the operand size.

B: Byte

W: Word

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