7643 datasheet(261/424 Pages) RENESAS

261 / 424 page

Rev.2.00

Aug 28, 2006

page 140 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.36 Control procedure

Device • address receive routine

IN_CSR (Address 5916),bit0 ?

No receive data in FIFO0

Branch to processing routine of each standard request

RTS

USR_RAM,X

USBFIFO0

(Address 6016)

X = 8?

• 8th byte is stored?

• Set DATA_END bit to “1”

USBA (Address 5016)

• Set (low-order) and ignore (high-order)

IN_CSR

(Address 5916),bit6

• OUT_PKT_RDY flag cleared

Data receive in FIFO0

• USR_RAM: User defined RAM

8 bytes required.

USBINDEX

(Address 5816),bit0

• Endpoint 0 used

X+1

• X : Index register X

(1st byte of USR_RAM)?

=“0516” (SET_ADDRESS request received)

(2nd byte of USR_RAM)

IN_CSR

(Address 5916),bit3

(2nd byte of USR_RAM) = 0 ?

Y: non-zero address

N: new address

Wait the end of status phase

IN_CSR

(Address 5916),bit6

IN_CSR

(Address 5916),bit3

Wait the end of status phase

USBA (Address 5016)

(2nd byte of USR_RAM)

(Set endpoint0 in the interrupt routine.)

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