7643 datasheet(305/424 Pages) RENESAS

305 / 424 page

Rev.2.00

Aug 28, 2006

page 184 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.8 External device connection

AB0 to AB7

(Port P0)

(AB15)

ta(OE)

50 ns (max.)

AB8 to AB14

(Port P1)

(RD of 7643)

DB0 to DB7

(Port P2)

Lower address

Upper address

twl(RD)

(1 + 0.5) • 83.33 ns – 5 ns (min.)

tsu(DB-RD)

13 ns (min.)

“H” level

td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7643 group

twl(RD)

: RD pulse width of 7643 group

ta(OE)

: Output enable access time of M5M5256BP-10

tsu(DB-RD) : Data bus setup time before RD of 7643 group

f(XIN) = 24 MHz

Vcc = 5 V

td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.)

td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.)

AB0 to AB7

(Port P0)

AB8 to AB14

(Port P1)

(RD of 7643)

DB0 to DB7

(Port P2)

Lower address

Upper address

“H” level

tPHL

5.8 ns

(max.)

ta(OE)

50 ns (max.)

twl(RD)

(1 + 0.5) • 83.33 ns – 5 ns (min.)

tsu(DB-RD)

13 ns (min.)

td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7643 group

twl(RD)

: RD pulse width of 7643 group

tPHL

: Output delay time of 74F04

ta(OE)

: Output enable access time of M5M27C256AK-10

tsu(DB-RD) : Data bus setup time before RD of 7643 group

f(XIN) = 24 MHz

Vcc = 5 V

td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.)

td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.)

Fig. 2.8.11 Read cycle (OE access, SRAM)

Fig. 2.8.12 Read cycle (OE access, EPROM)

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