SPC574K72E5 datasheet(103/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

Figure 37. RMII serial management channel timing diagram

3.17.3.2

RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK

frequency.

Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance

is accounted for, and need not be subtracted from the 25 pF value. Care should be taken to align external load on MDIO

and MDC.

M11

MDC (output)

MDIO (output)

M12

M13

MDIO (input)

M10

M14

M15

Table 55. RMII receive signal timing(1)(2)

Symbol

Characteristic

Value

Unit

Min

Max

RXD[1:0], CRS_DV to REF_CLK setup

—

REF_CLK to RXD[1:0], CRS_DV hold

—

REF_CLK pulse width high

35%

65%

REF_CLK period

REF_CLK pulse width low

35%

65%

REF_CLK period

All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

RMII timing is valid only up to a maximum of 150 oC junction temperature.

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