SPC574K72E5 datasheet(107/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

3.17.4.2

TxD

Figure 42. TxD signal

dCCTxD50%

TxD

dCCTxDFALL

dCCTxDRISE

50 %

80 %

Table 58. TxD output characteristics(1)(2)

Symbol

Characteristic

Value

Unit

Min

Max

dCCTxAsym

Asymmetry of sending CC at 25 pF load

(= dCCTxD50%  100 ns)

–2.45

2.45

dCCTxDRISE25+dCCTxDFALL25 CC

Sum of Rise and Fall time of TxD signal at the

output pin(3),(4)

—9(5)

D—

9(6)

dCCTxD01

Sum of delay between Clk to Q of the last FF and

the final output buffer, rising edge

—25

dCCTxD10

Sum of delay between Clk to Q of the last FF and

the final output buffer, falling edge

—25

TxD pin load maximum 25 pF.

Specifications valid according to FlexRay EPL 3.0.1 standard with 20%–80% levels and a 10pF load at the end of a

50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications.

Pad configured as VERY STRONG.

Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire

temperature range of the device has been taken into account.

5. VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF

6. VDD_HV_IO = 3.3 V ± 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF

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