MC68HC908AP16CFB datasheet(122/440 Pages) MOTOROLA

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Clock Generator Module (CGM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

122

MOTOROLA

8.5.4 PLL VCO Range Select Register

The PLL VCO range select register (PMRS) contains the programming

information required for the hardware configuration of the VCO.

VRS[7:0] — VCO Range Select Bits

These read/write bits control the hardware center-of-range linear

multiplier L which, in conjunction with E (See 8.3.3 PLL Circuits,

8.3.6 Programming the PLL, and 8.5.1 PLL Control Register.),

controls the hardware center-of-range frequency, fVRS. VRS[7:0]

cannot be written when the PLLON bit in the PCTL is set. (See 8.3.7

Special Programming Exceptions.) A value of $00 in the VCO

range select register disables the PLL and clears the BCS bit in the

PLL control register (PCTL). (See 8.3.8 Base Clock Selector Circuit

and 8.3.7 Special Programming Exceptions.). Reset initializes the

NOTE:

The VCO range select bits have built-in protection such that they cannot

be written when the PLL is on (PLLON = 1) and such that the VCO clock

cannot be selected as the source of the base clock (BCS = 1) if the VCO

range select bits are all clear.

The PLL VCO range select register must be programmed correctly.

Incorrect programming can result in failure of the PLL to achieve lock.

Address:

$003A

Bit 7

Bit 0

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

010

Figure 8-8. PLL VCO Range Select Register (PMRS)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 122 Page - Motorola, Inc

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