MC68HC908AP16CFB datasheet(121/440 Pages) MOTOROLA

121 / 440 page

Clock Generator Module (CGM)

CGM Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

121

8.5.3 PLL Multiplier Select Registers

The PLL multiplier select registers (PMSH and PMSL) contain the

programming information for the modulo feedback divider.

MUL[11:0] — Multiplier Select Bits

These read/write bits control the modulo feedback divider that selects

the VCO frequency multiplier N. (See 8.3.3 PLL Circuits and 8.3.6

Programming the PLL.) A value of $0000 in the multiplier select

registers configure the modulo feedback divider the same as a value

of $0001. Reset initializes the registers to $0040 for a default multiply

value of 64.

NOTE:

The multiplier select bits have built-in protection such that they cannot

be written when the PLL is on (PLLON = 1).

Address:

$0038

Bit 7

Bit 0

Read:

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

000

= Unimplemented

Figure 8-6. PLL Multiplier Select Register High (PMSH)

Address:

$0039

Bit 7

Bit 0

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

010

Figure 8-7. PLL Multiplier Select Register Low (PMSL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 121 Page - Motorola, Inc

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