MC68HC908AP16CFB datasheet(117/440 Pages) MOTOROLA

117 / 440 page

Clock Generator Module (CGM)

CGM Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

117

8.5.1 PLL Control Register

The PLL control register (PCTL) contains the interrupt enable and flag

bits, the on/off switch, the base clock selector bit, the prescaler bits, and

the VCO power-of-two range selector bits.

PLLIE — PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate an interrupt request

when the LOCK bit toggles, setting the PLL flag, PLLF. When the

AUTO bit in the PLL bandwidth control register (PBWC) is clear,

PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE

bit.

1 = PLL interrupts enabled

0 = PLL interrupts disabled

PLLF — PLL Interrupt Flag Bit

This read-only bit is set whenever the LOCK bit toggles. PLLF

generates an interrupt request if the PLLIE bit also is set. PLLF

always reads as logic 0 when the AUTO bit in the PLL bandwidth

control register (PBWC) is clear. Clear the PLLF bit by reading the

PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition

0 = No change in lock condition

NOTE:

Do not inadvertently clear the PLLF bit. Any read or read-modify-write

operation on the PLL control register clears the PLLF bit.

Address:

$0036

Bit 7

Bit 0

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

001

= Unimplemented

Figure 8-4. PLL Control Register (PCTL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 117 Page - Motorola, Inc

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