MC68HC908AP16CFB datasheet(116/440 Pages) MOTOROLA

116 / 440 page

Clock Generator Module (CGM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

116

MOTOROLA

8.4.6 CGM VCO Clock Output (CGMVCLK)

CGMVCLK is the clock output from the VCO.

8.4.7 CGM Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal goes to the SIM,

which generates the MCU clocks. CGMOUT is a 50 percent duty cycle

clock running at twice the bus frequency. CGMOUT is software

programmable to be either the oscillator output, CGMXCLK, divided by

two or the divided VCO clock, CGMPCLK, divided by two.

8.4.8 CGM CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

8.5 CGM Registers

The following registers control and monitor operation of the CGM:

•

PLL control register (PCTL)

(See 8.5.1 PLL Control Register.)

•

PLL bandwidth control register (PBWC)

(See 8.5.2 PLL Bandwidth Control Register.)

•

PLL multiplier select registers (PMSH and PMSL)

(See 8.5.3 PLL Multiplier Select Registers.)

•

PLL VCO range select register (PMRS)

(See 8.5.4 PLL VCO Range Select Register.)

•

PLL reference divider select register (PMDS)

(See 8.5.5 PLL Reference Divider Select Register.)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 116 Page - Motorola, Inc