MC68HC908AP16CFB datasheet(112/440 Pages) MOTOROLA

112 / 440 page

Clock Generator Module (CGM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

112

MOTOROLA

9. Program the PLL registers accordingly:

a. In the PRE bits of the PLL control register (PCTL), program

the binary equivalent of P.

b. In the VPR bits of the PLL control register (PCTL), program

the binary equivalent of E.

c. In the PLL multiplier select register low (PMSL) and the PLL

multiplier select register high (PMSH), program the binary

equivalent of N.

d. In the PLL VCO range select register (PMRS), program the

binary coded equivalent of L.

e. In the PLL reference divider select register (PMDS), program

the binary coded equivalent of R.

NOTE:

The values for P, E, N, L, and R can only be programmed when the PLL

is off (PLLON = 0).

Table 8-1 provides numeric examples (numbers are in hexadecimal

notation):

Table 8-1. Numeric Examples

CGMVCLK

CGMPCLK

fBUS

fRCLK

8.0 MHz

2.0 MHz

32.768 kHz

9.8304 MHz

2.4576 MHz

32.768 kHz

12C

10.0 MHz

2.5 MHz

32.768 kHz

132

16 MHz

4.0 MHz

32.768 kHz

1E9

19.6608 MHz

4.9152 MHz

32.768 kHz

258

20 MHz

5.0 MHz

32.768 kHz

263

29.4912 MHz

7.3728 MHz

32.768 kHz

384

32 MHz

8.0 MHz

32.768 kHz

3D1

32 MHz

16 MHz

4.0 MHz

32.768 kHz

1E9

32 MHz

8 MHz

2.0 MHz

32.768 kHz

32 MHz

4 MHz

1.0 MHz

32.768 kHz

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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