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5238-DS03-405-R Datasheet(PDF) 23 Page - Broadcom Corporation.

Part # 5238-DS03-405-R
Description  10/100BASE-TX Octal Transceiver
PDF  76 Pages
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Manufacturer  BOARDCOM [Broadcom Corporation.]
Direct Link  http://www.broadcom.com
Logo BOARDCOM - Broadcom Corporation.

5238-DS03-405-R Datasheet(HTML) 23 Page - Broadcom Corporation.

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Advance Data Sheet
BCM5238
1/31/03
Broa d c om Co rp o r a t i o n
Document
5238-DS03-405-R
Operational Description
Page 15
Se cti on 4: Op er a t ion a l D e s c r i p ti on
RESETTING THE BCM5238
There are two ways to reset each transceiver in the BCM5238. A hardware reset pin has been provided which resets all
internal nodes inside the chip to a known state. The reset pulse must be asserted for at least 2
µs. Hardware reset should
always be applied to a BCM5238 after power-up.
Each transceiver in the BCM5238 also has an individual software reset capability. To perform software reset, a 1 must be
written to bit 15 of the transceiver’s MII Control register (see “MII Control Register” on page 29). This bit is self-clearing,
meaning that a second write operation is not necessary to end the reset. There is no effect if a 0 is written to the MII Control
Register Reset bit.
PHY ADDRESS
Each transceiver in the BCM5238 has a unique PHY address for MII management. The PHY address is determined by the
using the base address, which is input on the PHYAD[4:0] pins. The following shows the addressing of the eight PHYs.
PHY0 = PHYAD + 0, PHY1 = PHYAD + 1,... PHY7 = PHYAD + 7
Every time an MII write or read operation is executed, the transceiver compares the PHY address with its own PHY address
definition. The operation is executed only when the addresses match.
LOOPBACK MODE
The loopback mode allows in-circuit testing of the BCM5238 chip. All packets sent in through the TXD pins are looped-back
internally to the RXD pins, and are not sent out to the cable. Incoming packets on the cable are ignored.
The loopback mode may be entered by writing a 1 to bit 14 of the MII Control register or by writing a 1 to bit 8 and bit 7 of
shadow register 1Dh. To resume normal operation, the bits must be 0.
FULL-DUPLEX MODE
The BCM5238 supports full-duplex operation. While in full-duplex mode, a transceiver can simultaneously transmit and
receive packets on the cable. By default, each transceiver in the BCM5238 powers up in half-duplex mode.
When auto-negotiation is disabled, full-duplex operation can be enabled either by a pin (FDXEN) or by an MII register bit
(register 0, bit 8).



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