5238-DS03-405-R datasheet(60/76 Pages) BOARDCOM

60 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 52

Auxiliary Mode 4 (PHY 7 of 8) Register (Shadow Register)

Document

5238-DS03-405-R

AUXILIARY MODE 4 (PHY 6 OF 8) REGISTER (SHADOW REGISTER)

See“LED Display Output Modes” on page 18 for details of all available configuration.

AUXILIARY MODE 4 (PHY 7 OF 8) REGISTER (SHADOW REGISTER)

See“LED Display Output Modes” on page 18 for details of all available configuration.

Table 44: Auxiliary Mode 4 (PHY 6 of 8) Register (Shadow Register 26d, 1Ah)

BIt

Name

R/W

Description

Default

15:6

Reserveda

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

–

00110

00000

5:3

Extended LED2 for PHY 6 of

8 Select[2:0]

R/W

Configuration bits for LED2 output for PHY 6 of 8

(see “LED Display Output Modes” on page 18 for

details)

000

2:0

Extended LED1 for PHY 6 of

8 Select[2:0]

R/W

Configuration bits for LED1 output for PHY 6 of 8

(see “LED Display Output Modes” on page 18 for

details)

000

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). MII shadow register bank 1 is

accessed by setting MII register 1Fh bit 7 to a 1.

Table 45: Auxiliary Mode 4 (PHY 7 of 8) Register (Shadow Register 26d, 1Ah)

BIt

Name

R/W

Description

Default

15:6

Reserveda

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

–

00110

00000

5:3

Extended LED2 for PHY 7 of

8 Select[2:0]

R/W

Configuration bits for LED2 output for PHY 7 of 8

(see “LED Display Output Modes” on page 18 for

details)

000

2:0

Extended LED1 for PHY 7 of

8 Select[2:0]

R/W

Configuration bits for LED1 output for PHY 7 of 8

(see “LED Display Output Modes” on page 18 for

details)

000

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). MII shadow register bank 1 is

accessed by setting MII register 1Fh bit 7 to a 1.

5238-DS03-405-R Datasheet(PDF) 60 Page - Broadcom Corporation.

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