5238-DS03-405-R datasheet(62/76 Pages) BOARDCOM

62 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 54

Auxiliary Status 3 Register (Shadow Register)

Document

5238-DS03-405-R

ADC Peak Amplitude[5:0]. The BCM5238 returns the 6-bit peak amplitude of the ADC seen during this link.

APD Enable. When in normal mode, if this bit is set to a 1, the BCM5238 enters auto power-down mode. If this bit is set and

the link is lost, the BCM5238 enters low power-down mode. When energy is detected, the device enters full power mode.

Otherwise, it wakes up after either 2.5 seconds or 5.0 seconds, as determined by the APD Sleep Timer bit. When the

BCM5238 wakes up, it sends link pulses and also monitors energy. If the link partner’s energy is detected, the BCM5238

device continues to stay in wake-up mode for a duration determined by the APD wake-up timer before going to low power

mode.

APD Sleep Timer. This bit determines how long the BCM5238 stays in low power mode before waking up. If this bit is a 0,

the BCM5238 device waits approximately 2.5 seconds before waking up. Otherwise, it wakes up after approximately 5.0

seconds.

APD Wake-Up Timer[3:0]. This counter determines how long the BCM5238 stays in wake-up mode before going to low

power mode. This value is specified in 40-millisecond increments from 0 to 600 milliseconds. A value of 0 forces the

BCM5238 to stay in low power mode indefinitely. In this case, the BCM5238 requires a hard reset to return to normal mode.

AUXILIARY STATUS 3 REGISTER (SHADOW REGISTER)

Noise[7:0]. The BCM5238 provides the current mean-squared error value for noise when a valid link is established.

FIFO Consumption[3:0]. The BCM5238 indicates the number of nibbles of FIFO currently used.

011

60 to < 80

100

80 to < 100

101

100 to < 120

110

120 to < 140

111

> 140

Table 49: Auxiliary Status 3 Register (Shadow Register 28d, 1Ch)

BIt

Name

R/W

Description

Default

15:8

Noise[7:0]

R/O

Current mean-squared error value, valid only if link is

established

00h

7:4

Reserveda

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

–

000h

3:0

FIFO Consumption[3:0]

R/O

Currently utilized number of nibbles in the receive

FIFO

0000

Note: MII shadow register bank 1 is accessed by setting MII register 1Fh bit 7 to a 1.

Table 48: 100-TX Port Cable Length (Cont.)

Cable Length 100X[2:0]

Cable Length in Meters

5238-DS03-405-R Datasheet(PDF) 62 Page - Broadcom Corporation.

5238-DS03-405-R Datasheet(HTML) 62 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL