5238-DS03-405-R datasheet(52/76 Pages) BOARDCOM

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BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 44

Auxiliary Control/Status Register

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5238-DS03-405-R

AUXILIARY MODE 2 REGISTER

10BT Dribble Bit Correct. When enabled, the PHY rounds-down to the nearest nibble when dribble bits are present on the

10BASE-T input stream.

Jumbo Packet Mode. When enabled, the 100BASE-X unlock timer changes to allow long packets. See Table 4 on page 17

for details.

Jumbo Packet FIFO Enable. When enabled, the receive FIFO doubles from 7 nibbles to 14 nibbles. The Jumbo Packet

FIFO Enable bit should be set to a 1 when jumbo packet mode is enabled. See Table 3 on page 17 for details.

Block 10BT Echo Mode. When enabled, during 10BASE-T half-duplex transmit operation, the TXEN signal does not echo

onto the RXDV signal. The TXEN echoes onto the CRS signal and the CRS deassertion directly follows the TXEN

deassertion.

Traffic Meter LED Mode. When enabled, the Activity LEDs (ACTLED and FDXLED if full-duplex LED and interrupt LED

modes are not enabled) does not blink based on the internal LED clock (approximately 80 ms on time). Instead, they blink

based on the rate of receive and transmit activity. Each time a receive or transmit operation occurs, the LED turns on for a

minimum of 5 ms. During light traffic, the LED blinks at a low rate, while during heavier traffic the LEDs remain on.

Serial LED Mode. When enabled, normal serial LED mode is enabled. Serial LED mode can also be enabled through

hardware during power-on reset. Note that this bit is available only in PHY 1 of 8. This bit in all other PHYs are reserved.

Activity LED Force On. When asserted, the activity LEDs (ACTLED and FDXLED if full-duplex LED and interrupt LED

modes are not enabled) are turned on. This bit has a higher priority than the Activity LED Force Inactive, bit 4, Register 1Dh.

Table 34: Auxiliary Mode 2 Register (Address 27d, 1Bh)

BIt

Name

R/W

DESCRIPTION

Default

15:12

Reserveda

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

––

10BT Dribble Bit Correct

R/W

1 = Enable, 0 = Disable

Jumbo Packet Mode

R/W

1 = Enable, 0 = Disable

Jumbo Packet FIFO Enable

R/W

1 = Enable, 0 = Disable

Reserveda

––

Block 10BT Echo Mode

R/W

1 = Enable, 0 = Disable

Traffic Meter LED Mode

R/W

1 = Enable, 0 = Disable

Activity LED Force On

R/W

1 = ON, 0 = Normal operation

Serial LED Mode

(this bit is available only in

PHY 1 of 8)

R/W

1 = Enable Serial LED mode

Reserveda

––

Activity/Link LED Mode

R/W

1 = Enable, 0 = Disable

Qual Parallel Detect Mode

R/W

1 = Enable, 0 = Disable

Reserveda

––

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

5238-DS03-405-R Datasheet(PDF) 52 Page - Broadcom Corporation.

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