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5238-DS03-405-R Datasheet(PDF) 30 Page - Broadcom Corporation.

Part # 5238-DS03-405-R
Description  10/100BASE-TX Octal Transceiver
PDF  76 Pages
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Manufacturer  BOARDCOM [Broadcom Corporation.]
Direct Link  http://www.broadcom.com
Logo BOARDCOM - Broadcom Corporation.

5238-DS03-405-R Datasheet(HTML) 30 Page - Broadcom Corporation.

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BCM5238
Advance Data Sheet
1/31/03
Broa d c om Co rp o r a t i o n
Page 22
Serial LED Mode
Document
5238-DS03-405-R
PARALLEL LED MODE
There are two LED pins, LED1 and LED2, for each port. Each can be individually configured to output one of many PHY
status or forced signals. These two LEDs are referred to as parallel LEDs and they are always enabled. For unmanaged
system design using the BCM5238, the parallel LED pins for each port can be programmed through hardware during power-
on reset by pull-down or pull-up combinations of LED1{1:6} pins. See Table 12 and Table 13 for details.
Software configuration of LED1 and LED2 is accomplished through MII shadow register 1Ah, PHY 1, bits [5:0] if parallel LED
Select Enable, bit 9, of MII Shadow Register 1Ah, PHY 1 is set to a 1. The shadow register is enabled by setting bit 7 of MII
register 1Fh. See Table 12 and Table 13 for details.
Note that in this mode, after the programming specified in Table 12 and Table 13 (either through power-on reset or through
software), LED1 and LED2 outputs provide the same status outputs for all eight ports.
Table 12: Parallel LED Mode LED1 Selection
LED1{3:1}
MII Shadow Register 1Ah, PHY 1, Bits [2:0]
Value
LED1 Selection
Power-on LED1 Select Bits [2:0]
LED1 Select [2:0]
0
Link
1
Speed
2
Activity
3
Full-duplex
4Transmit
5Receive
6
Interrupt
7
Collision
Note: MII shadow register is accessed by setting MII register 1Fh bit 7 to a 1.
Table 13: Parallel LED Mode LED2 Selection
LED1{6:4}
MII SHADOW REGISTER 1Ah, PHY 1, BITS [5:3] Value
LED2 Selection
Power-on LED2 Select Bits [2:0]
LED2 Select [2:0]
0
Speed
1Activity
2
Full-duplex
3
Transmit
4
Receive
5
Interrupt
6
Collision
7Link
Note: MII shadow register is accessed by setting MII register 1Fh bit 7 to a 1.



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