5238-DS03-405-R datasheet(14/76 Pages) BOARDCOM

14 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 6

Source Synchronous SMII (SSSMII) Interface

Document

5238-DS03-405-R

INTERRUPT MODE

The BCM5238 can be programmed to provide an interrupt output consisting of an OR of the eight interrupts, one from each

PHY. The interrupt feature is disabled by default. The interrupt capability is enabled by setting MII register 1Ah, bit 14. The

status of each interrupt source is also reflected in register 1Ah, bits 1, 2 and 3. The sources of interrupt are change in link,

speed or full-duplex status. If any type of interrupt occurs, the Interrupt Status bit, register 1Ah, bit 0 is set.

In addition, each transceiver has its own register controlling the interrupt function.

If the interrupt enable bit is set to 0, no status bits sets and no interrupts are generated. If the interrupt enable bit is set to 1,

the following conditions apply:

•

If mask status bits are set to 0 and the interrupt mask is set to 1, status bits are set, but no interrupts are generated.

•

If mask status bits are set to 0 and the interrupt mask is set to 0, status bits and interrupts are available.

•

If mask status bits are set to 1 and the interrupt mask is set to 0, no status bits and no interrupts are available.

Changes from active to inactive, or vice versa, cause an interrupt. Setting register 1Ah, bit 8 high masks all interrupts,

regardless of the settings of the individual mask bits.

5238-DS03-405-R Datasheet(PDF) 14 Page - Broadcom Corporation.