5238-DS03-405-R datasheet(45/76 Pages) BOARDCOM

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Advance Data Sheet

BCM5238

1/31/03

Broa d c om Co rp o r a t i o n

Document

5238-DS03-405-R

100BASE-X Auxiliary Control Register

Page 37

Transmit Disable. The transmitter may be disabled by writing a 1 to bit 13 of MII register 10h. The transmitter output (TD±)

is forced into a high impedance state.

Bypass 4B5B Encoder/Decoder. The 4B5B encoder and decoder may be bypassed by writing a 1 to bit 10 of MII register

10h. The transmitter sends 5B codes from the TXER and TXD signals directly to the scrambler. TXEN must be active and

frame encapsulation (insertion of J/K and T/R codes) is not performed. The receiver places descrambled and aligned 5B

codes onto the RXER and RXD signals. CRS is asserted when a valid frame is received.

Bypass Scrambler/Descrambler. The stream cipher function may be disabled by writing a 1 to bit 9 of MII register 10h.

The stream cipher function may be reenabled by writing a 0 to this bit.

Bypass NRZI Encoder/Decoder. The NRZI encoder and decoder can be bypassed by writing a 1 to bit 8 of MII register

10h, causing 3-level NRZ data to be transmitted and received on the cable. Normal operation (3-level NRZI encoding and

decoding) may be re-enabled by writing a 0to this bit.

Bypass Receive Symbol Alignment. Receive symbol alignment may be bypassed by writing a 1 to bit 7 of MII register 10h.

When used in conjunction with the bypass 4B5B encoder/decoder bit, unaligned 5B codes are placed directly on the RXER

and RXD signals.

Baseline Wander Correction Disable. The baseline wander correction circuit may be disabled by writing a 1 to bit 6 of MII

Extended FIFO Enable. Controls the extended receive FIFO mechanism. This bit may have to be set if the Jumbo Packet

Enable bit is set. See Table 3 on page 17 for details.

Bypass 4B5B Encoder/Decoder

R/W

1 = Transmit and receive 5B codes over SMII pins

0 = Normal SMII interface

Bypass Scrambler/Descrambler

R/W

1 = Scrambler and descrambler disabled

0 = Scrambler and descrambler enabled

Bypass NRZI Encoder/Decoder

R/W

1 = NRZI encoder and decoder is disabled

0 = NRZI encoder and decoder is enabled

Bypass Receive Symbol Alignment

R/W

1 = 5B receive symbols not aligned

0 = Receive symbols aligned to 5B boundaries

Baseline Wander Correction Disable

R/W

1 = Baseline Wander Correction disabled

0 = Baseline Wander Correction enabled

FEF Enable

R/W

1 = Far End Fault enabled

0 = Far End Fault disabled

4:3

Reserveda

––

Extended FIFO Enable

R/W

1 = Extended FIFO mode, 0 = Normal FIFO mode

1:00

Reserveda

––

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

Table 26: 100-BASE-X Auxiliary Control register (Address 16d, 10h) (Cont.)

Bit

Name

R/W

Description

Default

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

5238-DS03-405-R Datasheet(PDF) 45 Page - Broadcom Corporation.

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