5238-DS03-405-R datasheet(12/76 Pages) BOARDCOM

12 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 4

Multimode Transmit DAC

Document

5238-DS03-405-R

modes. The input data streams are sampled by the recovered clock from each port and fed synchronously to the respective

digital adaptive equalizer.

MULTIMODE TRANSMIT DAC

The multimode transmit digital to analog converter (DAC) transmits MLT3-coded symbols in 100BASE-TX mode and

Manchester-coded symbols in 10BASE-T mode. It performs programmable edge-rate control in TX mode, which decreases

unwanted high-frequency signal components, thus reducing EMI. High-frequency pre-emphasis is performed in 10BASE-T

mode. The transmit DAC uses a current drive output that is well balanced and produces very low noise transmit signals.

STREAM CIPHER

In 100BASE-TX mode, the transmit data stream is scrambled in order to reduce radiated emissions on the twisted pair cable.

The data is scrambled by exclusive ORing the NRZ signal with the output of an 11-bit-wide linear feedback shift register

(LFSR), which produces a 2047-bit non-repeating sequence. The scrambler reduces peak emissions by randomly spreading

the signal energy over the transmit frequency range, and eliminating peaks at certain frequencies. Signal energy is spread

further by using unique seeds to generate a different non-repeating sequence for each of the eight ports.

The receiver descrambles the incoming data stream by exclusive ORing it with the same sequence generated at the

transmitter. The descrambler detects the state of the transmit LFSR by looking for a sequence representing consecutive idle

codes. The descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code-groups.

The receiver does not attempt to decode the data stream unless the descrambler is locked. Once locked, the descrambler

continuously monitors the data stream to make sure that it has not lost synchronization. The receive data stream is expected

to contain inter-packet idle periods. If the descrambler does not detect enough idle codes within 724

µs, it becomes

unlocked, and the receive decoder is disabled. If the receiver is put into Token Ring mode (see bit 10, register 1Bh), the

descrambler monitors the receiver for 5792

µs before unlocking. The descrambler is always forced into the unlocked state

when a link failure condition is detected.

Stream cipher scrambling/descrambling is not used in 10BASE-T mode.

MII MANAGEMENT

Management of each transceiver within the BCM5238 remains the same as it was under the MII specification. Each PHY

contains an independent set of MII management registers. They share a single MDC/MDIO serial interface. Each transceiver

has a unique address and must be accessed individually. The common base address for the group of eight individual

transceivers is defined by configuring the five external PHYAD address input pins.

SMII INTERFACE

The objective of this interface is to reduce the number of pins required to interconnect the MAC and the PHY. This is

accomplished by clocking data and control signals in and out of each PHY on a pair of pins at a rate of 125 MHz.

5238-DS03-405-R Datasheet(PDF) 12 Page - Broadcom Corporation.