5238-DS03-405-R datasheet(16/76 Pages) BOARDCOM

16 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 8

Hardware Signal Definition Table

Document

5238-DS03-405-R

Clock Signal

T15

REF_CLK

Reference Clock Input. This pin must be driven with a

continuous 125-MHz clock. It provides timing for RXD0,

TXD0, and their associated clocks and SYNC signals.

Accuracy shall be

±50 ppm, with a duty cycle between 35%

and 65% inclusive.

PHY Control and Mode Signals

C16

102

RESET

IPU

Reset. Active Low. Resets the BCM5238. Pin not included

in NAND chain.

N15

127

F100

IPU

10/100 Mode Select. When high and ANEN is low, all

transceivers are forced to 100BASE-X operation. When low

and ANEN is low, all transceivers are forced to 10BASE-T

operation. When ANEN is high, F100 has no effect on the

operation.

M13

126

ANEN

IPU

Auto-Negotiation Enable. Active high. When pulled high,

auto-negotiation begins immediately after reset. When low,

auto-negotiation is disabled after reset. Auto-negotiation

can be enabled under software control (register 0, bit 12) if

auto-negotiation is enabled through hardware.

C15

101

FDXEN

IPD

Full-Duplex Mode Enable. The FDXEN pin is logically

ORed with an MII control bit to generate an internal full-

duplex enable signal. When FDXEN is high, the BCM5238

may operate in full-duplex mode as determined by auto-

negotiation. When FDXEN is low, the internal control bit

(register 0, bit 8) determines the full-duplex operating

mode. Initial value of the internal control bit is zero.

F05

MDIX_DIS

IPD

HP Auto-MDIX Disable. Active high. When pulled high

during reset, automatic TX cable swap detection function of

the BCM5238 is disabled. Leave this pin unconnected for

normal operation.

F04

117

TESTEN

IPD

Test Enable. Active high test control input used along with

PHYAD[4:0] to select the NAND-chain test mode. This test

mode is latched when TESTEN is pulsed high, then low,

with PHYAD[4:0] = 10111. This pin is not included in the

NAND chain and must be pulled low or left unconnected

during normal operation.

K02

INTR/

SLED_DO

OOD

PHY Interrupt. Active low output. This pin becomes

interrupt output if SER_EN pin is low during power-on reset.

SLED_DO. Serial LED Data. Active low serial LED data.

Pin-71 becomes serial LED data output if SERIAL_EN pin

is high during power-on reset. See “LED Display Output

Modes” on page 18 for details.

Table 2: Pin Definitions (Cont.)

BCM5238B

BCM5238U

Pin Label

I/O

Description

5238-DS03-405-R Datasheet(PDF) 16 Page - Broadcom Corporation.

5238-DS03-405-R Datasheet(HTML) 16 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL