| Electronic Components Datasheet Search |
|
5238-DS03-405-R Datasheet(PDF) 24 Page - Broadcom Corporation. |
|
|
|||||||||||||||||||||||||||||
5238-DS03-405-R Datasheet(HTML) 24 Page - Broadcom Corporation. |
|
24 / 76 page ![]() BCM5238 Advance Data Sheet 1/31/03 Broa d c om Co rp o r a t i o n Page 16 10BASE-T Mode Document 5238-DS03-405-R When auto-negotiation is enabled, full-duplex capability is advertised by default but can be overridden by a write to the Auto- Negotiation Advertisement register (04h). 10BASE-T MODE The same magnetics module is used to interface the twisted-pair cable in 10BASE-T mode and in 100BASE-TX mode. The data is two-level Manchester coded instead of three-level MLT3, and no scrambling/descrambling or 4B5B coding is performed. ISOLATE MODE Each transceiver in the BCM5238 can be isolated from the RMII/SMII/S3MII interface. When a transceiver is put into isolate mode, all RMII/SMII/S3MII input pins (TXD0, SSYNCS, SMII_TXC) are ignored and all SMII/S3MII output pins (RXD0, SSMII_RSYNC, SSMII_RXC) are set at high impedance. MII management pins (MDC, MDIO,) and analog TD±, RD± pins operate normally. Writing a 1 to bit 10 of the MII Control register 0 puts the port into isolate mode. Writing a 0 to the same bit removes it from isolate mode. Upon resetting the chip or resetting the isolated port, the isolate mode is off. SUPER ISOLATE MODE When the chip is in super isolate mode, in addition to isolate mode actions, the chip also sets the analog TD± pins to high impedance. Writing a 1 to bit 3 of the MII register 1Eh puts the port into super isolate mode. Writing a 0 to the same bit removes it from super isolate mode. Upon resetting the chip or resetting the isolated port, the super isolate mode is off. AUTO POWER-DOWN MODE The BCM5238 supports a low power mode called auto power-down mode. Auto power-down mode is enabled by setting bit 5 of shadow register 1Bh. When in this mode, the BCM5238 automatically enters the low power mode if the energy from the link partner is lost. Similarly, the next time energy is detected, the chip resumes full power mode. When the BCM5238 is in this low power mode, it wakes up after approximately 2.5 to 5.0 seconds, as determined by bit 4 of shadow register 1Bh, and sends a link pulse while monitoring energy from the link partner. If energy is detected, the BCM5238 enters full power mode and establishes link with the link partner. Otherwise, the wake-up mode continues for a duration of approximately 40– 600 ms, as determined by bits [3:0] of shadow register 1Bh before going to low power mode. See Table47onpage 53 for details of various bits. JUMBO PACKET MODE In 100BASE-X mode, the BCM5238 can support jumbo packet sizes. The size of the packet that can be handled reliably depends on the descrambler lock timer settings and the receive FIFO size. By default, the BCM5238 provides an effective 10 bits receive FIFO to accommodate the minor clock deviations of the link partner. Additionally , the BCM5238 incorporates |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |