5238-DS03-405-R datasheet(18/76 Pages) BOARDCOM

18 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 10

Hardware Signal Definition Table

Document

5238-DS03-405-R

H02

MASTERPHY/

SFRAME

I/OPD

Master PHY Address Mode. Active high. This forces PHY

address 0 to be a global write address for all PHYs within

the BCM5238. An active high during power-on reset selects

the master PHY address mode, while an active low or being

left unconnected selects the normal address mode.

SFRAME. Serial LED Frame. After power-on reset, this pin

sources the serial LED frame output signal if serial LED

mode is enabled.

LEDs and LED Control Signals

G03

SERIAL_EN

IPD

Serial LED Enable. Active high. Serial LED mode is

enabled if this pin is high and LC-SER_EN pin is low during

power-on reset. Serial LED mode and low cost serial LED

mode can not be active at the same time.

See “LED Display Output Modes” on page 18 for details.

G02

LC_SER_EN

IPU

Low Cost Serial LED Enable. Active high. Low cost serial

LED mode is enabled if this pin is high and SERIAL_EN pin

is high during power-on reset. Low cost serial LED mode

and serial LED mode cannot be active at the same time.

See “LED Display Output Modes” on page 18 for details.

F01, F02,

E01, E02,

P01, P02,

N02, N01

110, 111,

113, 114, 59,

60, 62, 63

LED1{1:8}

I/OPD

LED1[1:8]. Active low output. This is one of two available

parallel LED output signals. These pins are sampled during

power-on reset to set the default LED output for LED1 and

LED2. See “LED Display Output Modes” on page 18 for

details.

C04, E06,

D05, C05,

M07, N07,

M06, N06

105, 106,

108, 109, 53,

54, 57, 58

LED2{1:8}

OOD

LED2. Active low output. This is one of two available

parallel LED output signals. See “LED Display Output

Modes” on page 18 for details.

JTAG Signals

L02

121

TDI

IPU

Test Data Input. Single data input to the JTAG TAP

controller used to traverse the test-logic state machine.

Sampled on the rising edge of TCK. If unused, may be left

unconnected.

L03

123

TMS

IPU

Test Mode Select. Serial control input to the JTAG TAP

controller. Sampled on the rising edge of TCK. If unused,

can be left unconnected.

L05

122

TCK

IPU

Test Clock. Clock input used to synchronize the JTAG TAP

control and data transfers. If unused, can be left

unconnected.

K04

125

TDO

O3S

Test Data Output. Serial data output from the JTAG TAP

Controller. Updated on the falling edge of TCK. Actively

driven both high and low when enabled; high impedance

otherwise.

K05

124

TRST

IPU

Test Reset. Asynchronous active-low reset input to the

JTAG TAP Controller. Must be held low during power-up to

insure the TAP Controller initializes to the test-logic-reset

state; must be pulled low continuously when JTAG

functions are not used.

Power, Bias, and Reference Signals

A15

RDAC

DAC Bias Resistor. Adjusts the current level of each of the

transmit DACs. A resistor of 1.24 K

Ω±1% must be

connected between the RDAC pin and AGND.

Table 2: Pin Definitions (Cont.)

BCM5238B

BCM5238U

Pin Label

I/O

Description

5238-DS03-405-R Datasheet(PDF) 18 Page - Broadcom Corporation.

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