5238-DS03-405-R datasheet(38/76 Pages) BOARDCOM

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BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 30

MII Status Register

Document

5238-DS03-405-R

Isolate. Each individual PHY may be isolated from its Media Independent Interface by writing a 1 to bit 10 of the Control

Register. All RXD0{n} outputs is tri-stated and all TXD0{n} inputs are ignored. Since the MII management interface is still

active, the isolate mode may be cleared by writing a 0 to bit 10 of the control register, or by resetting the chip. When this bit

is read, it returns a 1 when the chip is in isolate mode, otherwise it returns a 0.

Restart Auto-Negotiation. Bit 9 of the Control Register is a self-clearing bit that allows the auto-negotiation process to be

restarted, regardless of the current status of the auto-negotiation state machine. In order for this bit to have an effect, auto-

negotiation must be enabled. Writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect.

Since the bit is self-clearing after only a few cycles, it always returns a 0 when read. The operation of this bit is identical to

bit 9 of the Auxiliary Multiple PHY Register.

Duplex Mode. By default, the BCM5248 powers up in half-duplex mode. The chip can be forced into full-duplex mode by

writing a 1 to bit 8 of the Control Register while auto-negotiation is disabled. Half-duplex mode can be resumed by writing a

0 to bit 8 of the Control Register, or by resetting the chip.

MII STATUS REGISTER

100BASE-T4 Capability. The BCM5248 is not capable of 100BASE-T4 operation and returns a 0 when bit 15 of the Status

100BASE-TX FDX Capability. The BCM5248 is capable of 100BASE-TX full-duplex operation and returns a 1 when bit 14

of the Status register is read.

Table 19: MII Status Register (Address 01d, 01h)

Bit

Name

R/W

Description

Default

100BASE-T4 Capability

0 = Not 100BASE-T4 capable

100BASE-TX FDX Capability

1 = 100BASE-TX full-duplex capable

100BASE-TX Capability

1 = 100BASE-TX half-duplex capable

10BASE-T FDX Capability

1 = 10BASE-T full-duplex capable

10BASE-T Capability

1 = 10BASE-T half-duplex capable

10:7

RESERVEDa

a. When writing to this register, preserve existing values of reserved bits by completing a Read/Modify Write.

–

0000

MF Preamble Suppression

R/W

1 = Preamble may be suppressed

0 = Preamble always required

Auto-Negotiation Complete

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

Reserved

Ignore when read

Auto-Negotiation Capability

1 = Auto-negotiation capable

0 = Not auto-negotiation capable

Link Status

1 = Link is up (link pass state)

0 = Link is down (link fail state)

Jabber Detect

1 = Jabber condition detected

0 = No jabber condition detected

Extended Capability

1 = Extended register capable

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

5238-DS03-405-R Datasheet(PDF) 38 Page - Broadcom Corporation.

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