5238-DS03-405-R datasheet(17/76 Pages) BOARDCOM

17 / 76 page

Advance Data Sheet

BCM5238

1/31/03

Broa d c om Co rp o r a t i o n

Document

5238-DS03-405-R

Hardware Signal Definition Table

Page 9

H01

SSSMII_DIS/

SLED_CLK

I/OPU

SSSMII Disable. Active high. When this pin is high or left

unconnected during power-on reset, the BCM5238 enables

the Serial Media Independent Interface mode (SMII).

When this pin is low (pull-down) during power-on reset, the

SMII source Synchronous SMII mode is enabled. When the

SMII Source Synchronous mode is enabled, the BCM5238

provides a source synchronous receive clock

(SSSMII_RXC) and a sync (SSSMII_RSYNC) for MAC to

use for receiving data from the PHY and the BCM5238 uses

SMII_TXC along with SSYNC to receive data from the

MAC.

SLED_CLK. Serial LED clock. After power-on reset, if

serial or low cost serial LED mode is enabled, this pin

sources the clock for serial data SLED_DO. See “LED

Display Output Modes” on page 18 for details.

E10

104

MODE_5228

IPU

BCM5228 Mode Select. Active high. During power-on if

this pin is left unconnected (or pull-up), the BCM5238 MII

registers values default to the BCM5228 MII register default

values. Otherwise, it defaults to the BCM5238 default

M08

LED1TO3

IPLL

LED1 to LED3 Option. Active low. When this pin is low, the

BCM5228 LED3 will be available on LED1. Refer to the

BCM5228 data sheet for hardware default and MII register

programming. Note that this option is available only in the

BCM5238B.

SMII and SSMII Signals

P15

SSYNC

IPD

SYNC. In SMII mode, this pin must be connected to a free

running sync pulse occurring 1 of every 10 clock cycles.

Data and controls are transferred through TXD and RXD

between respective MAC and PHY in default SMII mode. If

source synchronous enable, SSSMII_DIS, is low, then

SSYNC provides sync for TXD only and SSSMII_RSYNC

from the BCM5238 provides sync for RXD.

R16

SSSMII_RXC

O3S

SMII Source Synchronous Receive Clock. Optional 125-

MHz clock in SMII mode for MAC use to clock in RXD.

P16

SSSMII_RSYNC

O3S

SMII Source Synchronous SYNC. In SMII mode, this pin

provides a source synchronous SYNC pulse for MAC to

use for RXD if source synchronous is enabled.

T16

SSASMII_TXC

IPD

SMII Source Synchronous Transmit Clock.

125-MHz clock in SSSMII mode for BCM5238 to clock in

TXD if source synchronous mode is enabled.

MII Register Access Signals

J01

118

MDIO

I/OPU

Management Data I/O. This serial input/output bit is used

to read from and write to the MII registers. The data value

on the MDIO pin is valid and latched on the rising edge of

MDC.

K01

119

MDC

IPD

Management Data Clock. The MDC clock input must be

provided to allow MII management functions. Clock

frequencies up to 25 MHz are supported.

G05, H05,

H04, J05,

J03

47, 48, 49,

50, 51

PHYAD {4:0}

IPD

PHY ADdress Selects. These inputs set the base address

for MII management PHY addresses. Also serve as test

control inputs along with TESTEN to select the NAND-

chain test mode.

Table 2: Pin Definitions (Cont.)

BCM5238B

BCM5238U

Pin Label

I/O

Description

5238-DS03-405-R Datasheet(PDF) 17 Page - Broadcom Corporation.

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