ATTINY817-MFR. datasheet(18/492 Pages) MICROCHIP

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The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST

instructions as well as the LPM instruction. For LD/ST instructions, the Flash is mapped from address

0x8000. For the LPM instruction, the Flash start address is 0x0000.

The ATtiny417/817 also has a CRC module that is a master on the bus. If the CRC is configured to run in

the background it will read the Flash memory and can affect the program timing.

Related Links

Configuration Summary

NVMCTRL - Non Volatile Memory Controller

6.4

SRAM Data Memory

The 256B/512B SRAM is used for data storage and stack.

Related Links

AVR CPU

Stack and Stack Pointer

6.5

EEPROM Data Memory

The ATtiny417/817 has 128 bytes of EEPROM data memory, see Memory Map. The EEPROM memory

supports single byte read and write. The EEPROM is controlled by the Non-Volatile Memory Controller

(NVMCTRL).

Related Links

Memory Map

NVMCTRL - Non Volatile Memory Controller

6.6

User Row

In addition to the EEPROM, the ATtiny417/817 has one extra page of EEPROM memory that can be used

for firmware settings, the User Row (USERROW). This memory supports single byte read and write as

the normal EEPROM. The CPU can write and read this memory as normal EEPROM and the UPDI can

write and read it as a normal EEPROM memory if the part is unlocked. The User Row can also be written

by the UPDI when the part is locked. USERROW is not affected by a chip erase.

Related Links

Memory Map

NVMCTRL - Non Volatile Memory Controller

UPDI - Unified Program and Debug Interface

6.7

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be

read in both serial and parallel mode, also when the device is locked. The three bytes reside in a

separate address space. For the device the signature bytes are given in the following table.

ATtiny417/817

Datasheet Complete

DS40001901B-page 18

ATTINY817-MFR. Datasheet(PDF) 18 Page - Microchip Technology