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ATTINY817-MFR. Datasheet(PDF) 65 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 65 Page - Microchip Technology |
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65 / 492 page ![]() Value Name Description 0x0 OSC20M 16/20MHz internal oscillator 0x1 OSCULP32K 32KHz internal Ultra Low Power oscillator 0x2 XOSC32K 32.768kHz external crystal oscillator 0x3 EXTCLK External clock 10.5.2 Main Clock Control B Name: MCLKCTRLB Offset: 0x01 Reset: 0x11 Property: Configuration Change Protection Bit 7 6 5 4 3 2 1 0 PDIV[3:0] PEN Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 1 Bits 4:1 – PDIV[3:0]: Prescaler Division If the Prescaler Enable (PEN) bit is written to '1', these bits define the division ratio of the Main Clock prescaler. These bits can be written during run-time to vary the clock frequency of the system to suit the application requirements. User software must ensure a correct configuration of input frequency (CLK_MAIN) and Prescaler settings, such that the resulting frequency of CLK_PER never exceeds the allowed maximum (see Electrical Characteristics). Value Description Value Division 0x0 2 0x1 4 0x2 8 0x3 16 0x4 32 0x5 64 0x8 6 0x9 10 0xA 12 0xB 24 0xC 48 other Reserved Bit 0 – PEN: Prescaler Enable This bit must be written '1' to enable the prescaler. When enabled, the division ratio is selected by the PDIV bit field. When this bit is written to '0', the Main Clock will pass through undivided (CLK_PER=CLK_MAIN), regardless of the value of PDIV. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 65 |
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