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ATTINY817-MFR. Datasheet(PDF) 78 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 78 Page - Microchip Technology |
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78 / 492 page  When enabled, the External Reset requests a Reset as long as the RESET pin is low. The device will stay in Reset until RESET is high again. All logic is reset on external reset, except UPDI, TCD pin override settings and BOD configuration. All fuses are reloaded after the reset is released. Related Links FUSES - Configuration and User Fuses Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from software according to the programmed timeout period, a watchdog reset will be issued. See the WDT documentation for further details. All logic is reset on WDT reset, except UPDI, TCD pin override settings and BOD configuration. All fuses are reloaded after the reset is released. Related Links WDT - Watchdog Timer Universal Program Debug Interface (UPDI) Reset The UPDI contains a separate reset source that is used to reset the device during external programming and debugging. The reset source is accessible only from external debuggers and programmers. All logic is reset on UPDI reset, except the UPDI itself, TCD pin override settings and BOD configuration. All fuses are reloaded after the reset is released. See UPDI chapter on how to generate a UPDI reset request. Related Links UPDI - Unified Program and Debug Interface 12.3.2.2 Reset time The reset time can be split in two. The first part is when any of the Reset sources are active. This part depends on the input to the Reset sources. The external reset is active as long as the RESET pin is low, the power-on-reset (POR) and Brownout detector (BOD) is active as long as the supply voltage is below reset source threshold. When all the Reset sources are released an Internal reset initialization of the device is done. The time it take to do the Internal reset initialization is typical 250 µs. This time will be increased with the Start Up time given by the Start Up time fuse setting (SYSCFG1.SUT). The Internal reset initialization time will also increase if the CRC source is setup to run (SYSCFG0.CRCSRC). The additional Internal reset time will increase by 500 µs for each KB of memory that is checked. 12.3.3 Sleep Mode Operation The Reset Controller continues to operate in all active and sleep modes. 12.3.4 Configuration Change Protection This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four CPU instructions. It is possible to try writing to these registers any time, but the values are not altered. The following registers are under CCP: ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 78 |
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