ATTINY817-MFR. datasheet(91/492 Pages) MICROCHIP

91 / 492 page

Name:

STATUS

Offset: 0x01

Reset:

0x00

Property:

Bit

NMIEX

LVL1EX

LVL0EX

Access

Reset

Bit 7 – NMIEX: Non-Maskable Interrupt Executing

This flag is set if a non-maskable interrupt is executing. The flag is cleared when returning (RETI) from

the interrupt handler.

Bit 1 – LVL1EX: Level 1 Interrupt Executing

This flag is set when a priority level 1 interrupt is executing, or when the interrupt handler has been

interrupted by an NMI. The flag is cleared when returning (RETI) from the interrupt handler.

Bit 0 – LVL0EX: Level 0 Interrupt Executing

This flag is set when a priority level 0 interrupt is executing, or when the interrupt handler has been

interrupted by a priority level 1 interrupt or an NMI. The flag is cleared when returning (RETI) from the

interrupt handler.

13.5.3

Interrupt Priority Level 0

Name:

LVL0PRI

Offset: 0x02

Reset:

0x00

Property:

Bit

LVL0PRI[7:0]

Access

R/W

Reset

Bits 7:0 – LVL0PRI[7:0]: Interrupt Priority Level 0

When Round Robin is enabled (LVL0RR bit in CPUINT.CTRLA is '1'), this bit field stores the vector of the

last acknowledged priority level 0 (LVL0) interrupt. The stored vector will have the lowest priority next time

one or more LVL0 interrupts are pending.

If Round Robin is disabled (LVL0RR in CPUINT.CTRLA is '0'), the vector address based priority scheme

(lowest address has highest priority) is governing the priorities of LVL0 interrupt requests.

If a system Reset is asserted, the lowest interrupt vector address will have highest priority within the

LVL0.

13.5.4

Interrupt Vector with Priority Level 1

ATtiny417/817

Datasheet Complete

DS40001901B-page 91

ATTINY817-MFR. Datasheet(PDF) 91 Page - Microchip Technology

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