ATTINY817-MFR. datasheet(82/492 Pages) MICROCHIP

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13.

CPUINT - CPU Interrupt Controller

13.1

Features

•

Short and predictable interrupt response time

•

Separate interrupt configuration and vector address for each interrupt

•

Interrupt prioritizing by level and vector address

•

Two interrupt priority levels: 0 (normal) and 1 (high)

•

Higher priority for one interrupt

•

Optional round-robin priority scheme for priority level 0 interrupts

•

Non-maskable interrupts (NMI) for critical functions

•

Interrupt vectors optionally placed in the application section or the boot loader section

•

Selectable compact vector table

13.2

Overview

An interrupt request signals a change of state inside a peripheral, and can be used to alter program

execution. Peripherals can have one or more interrupts, and all are individually enabled and configured.

When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt

condition occurs.

The CPU Interrupt Controller (CPUINT) handles and prioritizes interrupt requests. When an interrupt is

enabled and the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the

interrupt's priority level and the priority level of any ongoing interrupts, the interrupt request is either

acknowledged or kept pending until it has priority. When an interrupt request is acknowledged by the

CPUINT, the program counter is set to point to the interrupt vector. The interrupt vector is normally a jump

to the interrupt handler (i.e., the software routine that handles the interrupt). After returning from the

interrupt handler, program execution continues from where it was before the interrupt occurred. One

instruction is always executed before any pending interrupt is served.

The CPUINT Status register (CPUINT.STATUS) contains state information that ensures that the CPUINT

returns to the correct interrupt level when the RETI (interrupt return) instruction is executed at the end of

an interrupt handler. Returning from an interrupt will return the CPUINT to the state it had before entering

the interrupt. CPUINT.STATUS is not saved automatically upon an interrupt request.

By default, all peripherals are priority level 0. It is possible to set one single interrupt vector to the higher

priority level 1. Interrupts are prioritized according to their priority level and their interrupt vector address.

Priority level 1 interrupts will interrupt level 0 interrupt handlers. Among priority level 0 interrupts, the

priority is determined from the interrupt vector address, where the lowest interrupt vector address has the

highest interrupt priority.

Optionally, a round-robin scheduling scheme can be enabled for priority level 0 interrupts. This ensures

that all interrupts are serviced within a certain amount of time.

Interrupt generation must be globally enabled by writing a '1' to the Global Interrupt Enable bit (I) in the

CPU Status register (CPU.SREG). This bit is not cleared when an interrupt is acknowledged.

ATtiny417/817

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