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ATTINY817-MFR. Datasheet(PDF) 83 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 83 Page - Microchip Technology |
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83 / 492 page  13.2.1 Block Diagram Figure 13-1. CPUINT Block Diagram INT REQ INT LEVEL INT ACK Peripheral 1 Peripheral n Interrupt Controller Sleep Controller CPU Priority Decoder STATUS CPU.SREG INT REQ INT REQ Global Interrupt Enable CPU "RETI" CPU INT ACK CPU INT REQ Wake-up LVL0PRI LVL1VEC 13.2.2 Signal Description Not applicable. 13.2.3 System Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. Table 13-1. CPUINT System Dependencies Dependency Applicable Peripheral Clocks Yes CLKCTRL I/O Lines and Connections No - Interrupts No - Events No - Debug Yes UPDI Related Links Debug Operation Clocks 13.2.3.1 Clocks This peripheral depends on the peripheral clock. Related Links CLKCTRL - Clock Controller 13.2.3.2 I/O Lines and Connections Not applicable. 13.2.3.3 Interrupts Not applicable. 13.2.3.4 Events Not applicable. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 83 |
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