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ATTINY817-MFR. Datasheet(PDF) 64 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 64 Page - Microchip Technology |
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64 / 492 page ![]() 10.4 Register Summary - CLKCTRL Offset Name Bit Pos. 0x00 MCLKCTRLA 7:0 CLKOUT CLKSEL[1:0] 0x01 MCLKCTRLB 7:0 PDIV[3:0] PEN 0x02 MCLKLOCK 7:0 LOCKEN 0x03 MCLKSTATUS 7:0 EXTS XOSC32KS OSC32KS OSC20MS SOSC 0x04 ... 0x0F Reserved 0x10 OSC20MCTRLA 7:0 RUNSTDBY 0x11 OSC20MCALIBA 7:0 CAL20M[5:0] 0x12 OSC20MCALIBB 7:0 LOCK TEMPCAL20M[3:0] 0x13 ... 0x17 Reserved 0x18 OSC32KCTRLA 7:0 RUNSTDBY 0x19 ... 0x1B Reserved 0x1C XOSC32KCTRLA 7:0 CSUT[1:0] SEL RUNSTDBY ENABLE 10.5 Register Description 10.5.1 Main Clock Control A Name: MCLKCTRLA Offset: 0x00 Reset: 0x00 Property: Configuration Change Protection Bit 7 6 5 4 3 2 1 0 CLKOUT CLKSEL[1:0] Access R/W R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – CLKOUT: System Clock Out When this bit is written to '1', the system clock is output to CLKOUT pin. When the device is in a sleep mode, there is no clock output unless a peripheral is using the system clock. Bits 1:0 – CLKSEL[1:0]: Clock Select This bit field selects the source for the Main Clock (CLK_MAIN). ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 64 |
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