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ATTINY817-MFR. Datasheet(PDF) 44 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 44 Page - Microchip Technology |
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44 / 492 page ![]() Only the number of bits required to address the available data memory including external memory (up to 64KB) is implemented for each device. Unused bits will always read as zero. The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. To prevent corruption when updating the Stack Pointer from software, a write to CPU.SPL will automatically disable interrupts for the next four instructions or until the next I/O memory write. Name: SP Offset: 0x0D Reset: 0xxxxx Property: - Bit 15 14 13 12 11 10 9 8 SP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 SP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bits 15:8 – SP[15:8]: Stack Pointer high byte These bits hold the MSB of the 16-bit register. Bits 7:0 – SP[7:0]: Stack Pointer low byte These bits hold the LSB of the 16-bit register. 8.7.3 Status Register The Status register contains information about the result of the most recently executed arithmetic or logic instruction. For details about the bits in this register and how they are affected by the different instructions, see the Instruction Set Summary. Name: SREG Offset: 0x0F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – I: Global Interrupt Enable Writing a '1' to this bit enable interrupts on the device. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 44 |
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