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ATTINY817-MFR. Datasheet(PDF) 41 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 41 Page - Microchip Technology |
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41 / 492 page ![]() 8.5.6 Accessing 16-bit Registers The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus. For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the low byte of the 16-bit register in the same clock cycle. For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the temporary register. This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing the register. Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers. The temporary registers can also be read and written directly from user software. 8.5.7 CCP - Configuration Change Protection System critical I/O register settings are protected from accidental modification. Flash self-programming (via store to NVM controller) is protected from accidental execution. This is handled globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible after the CPU writes a signature to the CCP register. The different signatures are listed in the description of the CCP register (CPU.CCP). There are two modes of operation: one for protected I/O registers, and one for the protected self- programming. Related Links CCP 8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers In order to write to registers protected by CCP, these steps are required: 1. The software writes the signature that enables change of protected I/O registers to the CCP bit field in the CPU.CCP register. 2. Within four instructions, the software must write the appropriate data to the protected register. Most protected registers also contain a write enable/change enable/lock bit. This bit must be written to '1' in the same operation as the data are written. The protected change is immediately disabled if the CPU performs write operations to the I/O register or data memory, if load or store accesses to Flash, NVMCTRL, EEPROM are conducted, or if the SLEEP instruction is executed. 8.5.7.2 Sequence for Execution of Self-Programming In order to execute self-programming (the execution of writes to the NVM controller's command register), these steps are required: 1. The software temporary enables self-programming by writing the SPM signature to the CCP register (CPU.CCP). ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 41 |
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