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ATTINY817-MFR. Datasheet(PDF) 90 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 90 Page - Microchip Technology |
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90 / 492 page ![]() 13.4 Register Summary - CPUINT Offset Name Bit Pos. 0x00 CTRLA 7:0 IVSEL CVT LVL0RR 0x01 STATUS 7:0 NMIEX LVL1EX LVL0EX 0x02 LVL0PRI 7:0 LVL0PRI[7:0] 0x03 LVL1VEC 7:0 LVL1VEC[7:0] 13.5 Register Description 13.5.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00 Property: Configuration Change Protection Bit 7 6 5 4 3 2 1 0 IVSEL CVT LVL0RR Access R/W R/W R/W Reset 0 0 0 Bit 6 – IVSEL: Interrupt Vector Select If boot section is defined, it will be placed before application section. The actual start address of the application section is determined by the BOOTEND Fuse. This bit is protected by the Configuration Change Protection mechanism. Value Description 0 Interrupt vectors are placed at the start of the application section of the Flash. 1 Interrupt vectors are placed at the start of the boot section of the Flash. Bit 5 – CVT: Compact Vector Table This bit is protected by the Configuration Change Protection mechanism. Value Description 0 Compact Vector Table function is disabled 1 Compact Vector Table function is enabled Bit 0 – LVL0RR: Round-Robin Priority Enable This bit is not protected by the Configuration Change Protection mechanism. Value Description 0 Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has highest priority. 1 Round Robin priority scheme is enabled for priority level 0 interrupt requests. 13.5.2 Status ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 90 |
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