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ATTINY817-MFR. Datasheet(PDF) 54 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 54 Page - Microchip Technology |
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54 / 492 page ![]() Name: CTRLB Offset: 0x01 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 BOOTLOCK APCWP Access R/W R/W Reset 0 0 Bit 1 – BOOTLOCK: Boot Section Lock Writing a '1' to this bit locks the boot section from read and instruction fetch. If this bit is '1', a read from the boot section will return '0'. A fetch from the boot section will also return 0 as instruction. This bit can only be written from the boot section. It can only be cleared to '0' by a Reset. This bit will only take effect when the boot section is left the first time after the bit is written. Bit 0 – APCWP: Application Code Section Write Protection Writing a '1' to this bit protects the application code section from further writes. This bit can only be written to '1', it is cleared to '0' only by Reset. 9.5.3 Status Name: STATUS Offset: 0x02 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 WRERROR EEBUSY FBUSY Access R R R Reset 0 0 0 Bit 2 – WRERROR: Write Error This bit will read '1' when a write error has happened. A write error could be writing to different sections before doing a page write or writing to a protected area. This bit is valid for the last operation. Bit 1 – EEBUSY: EEPROM Busy This bit will read '1' when the EEPROM is busy with a command. Bit 0 – FBUSY: Flash Busy This bit will read '1' when the Flash is busy with a command. 9.5.4 Interrupt Control ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 54 |
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