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ATTINY817-MFR. Datasheet(PDF) 35 Page - Microchip Technology |
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ATTINY817-MFR. Datasheet(HTML) 35 Page - Microchip Technology |
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35 / 492 page ![]() 8. AVR CPU 8.1 Features • 8-bit, high-performance AVR RISC CPU – 135 instructions – Hardware multiplier • 32 8-bit registers directly connected to the ALU • Stack in RAM • Stack pointer accessible in I/O memory space • Direct addressing of up to 64KB of unified memory – Entire Flash accessible with all LD/ST instructions • True 16-bit access to 16-bit I/O registers • Efficient support for 8-, 16-, and 32-bit arithmetic • Configuration Change Protection for system-critical features 8.2 Overview All AVR devices use the 8-bit AVR CPU. The CPU is able to access memories, perform calculations, control peripherals, and execute instructions in the program memory. Interrupt handling is described in a separate section. Related Links Memories NVMCTRL - Non Volatile Memory Controller CPUINT - CPU Interrupt Controller 8.3 Architecture In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 35 |
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