LE58QL022BVC datasheet(29/61 Pages) ZARLINK

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Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

Figure 19.

MPI Real-Time Data Register

a. Loop Detect Debounce Filter

Notes:

*Transparent latch: Output follows input when EN is high; ouput holds last state when EN is low.

Debounce counter: Output is high after counting to programmed (DSH) number of 1 ms clocks; counter is reset for CD1 input changes at 125 µs

sample period. DSH0 - DSH3 programmed value is common for all four channels, but debounce counter is separate per channel.

b. Ground-Key Filter

Notes:

Programmed value of GK0 - GK3 determines clock rate (1 - 15 ms) of six-state counter.

If GK value = 0, the counter is bypassed and no buffering occurs.

Six-state up/down counter: Counts up when input is high; counts down when input is low.

Output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero.

Real-Time Data Register Operation

To obtain time-critical data such as off/on-hook and ring trip information from the SLIC with a minimum of processor time and

effort, the QLSLAC device contains an 8-bit Real Time Data register. This register contains CDA and CDB bits from all four

channels. The CDA bit for each channel is a debounced version of the CD1 input. The CDA bit is normally used for hook switch.

The CDB bit for each channel normally contains the debounced value of the CD2 input bit; however, if the E1 multiplex operation

is enabled, the CDB bit will contain the debounced value of the CD1B bit. CD1 and CD2 can be assigned to off-hook, ring trip,

ground key signals, or other signals. Frame sync is needed for the debounce and the ground key signals. If Frame sync is not

provided, the real-time register will not work. The register is read using MPI Command 4D/4Fh, and may be read at any time

regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip, or ground key information for all four

channels to be obtained from the QLSLAC device with one read operation versus one read per channel. If these data bits are not

used for supervision information, they can be accessed on an individual channel basis in the same way as C3–C5; however, CD1

and CD1B will not be debounced.

Interrupt

In addition to the Real Time Data register, an interrupt signal has been implemented in the QLSLAC device. The interrupt signal

is an active Low output signal which pulls Low whenever the unmasked CD bits change state (Low to High or High to Low); or

whenever the transmit PCM data changes on a channel in which the Arm Transmit Interrupt (ATI) bit is on. The interrupt control

is shown in Figure 17. The interrupt remains Low until the appropriate register is read. This output can be programmed as TTL

or open drain. When an interrupt is generated, all of the unmasked bits in the Real Time Data register latch and remain latched

until the interrupt is cleared. The interrupt is cleared by reading the register with Command 4Fh, by writing to the interrupt mask

register (Command 6Ch), or by a reset. If any of the inputs to the unmasked bits in the Real Time Data register are different from

CD1

FS (8 kHz)

(0 – 15 ms)

RST

DSH0 – DSH3

Debounce Period

Debounce Counter

CDA

EN/HOLD

UP/DN

Ground-Key

Sampling Interval

GK0 – GK3

1 – 15 ms

1 kHz

Clock Divider

(1 – 15 ms

clock output)

GK = 0

MUX

CDB

Six-State

Up/Down

Counter

CD2 or CD1B

RST

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