LE58QL022BVC datasheet(19/61 Pages) ZARLINK

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Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

SWITCHING CHARACTERISTICS

The following are the switching characteristics over operating range (unless otherwise noted). Min and max values are valid for

all digital outputs with a 115 pF load, except CD1–C5 with a 30 pF load. (See Figure 11 and Figure 12 for the microprocessor

interface timing diagrams.)

Microprocessor Interface

PCM Interface

PCLK not to exceed 8.192 MHz.

No.

Symbol

Parameter

Min

Typ

Max

Unit

Note

tDCY

Data clock period

122

tDCH

Data clock HIGH pulse width

tDCL

Data clock LOW pulse width

tDCR

Rise time of clock

tDCF

Fall time of clock

tICSS

Chip select setup time, Input mode

tDCY–10

tICSH

Chip select hold time, Input mode

tDCH–20

tICSL

Chip select pulse width, Input mode

8tDCY

tICSO

Chip select off time, Input mode

2500

tIDS

Input data setup time

tIDH

Input data hold time

tOLH

SLIC output latch valid

2500

tOCSS

Chip select setup time, Output mode

tDCY–10

tOCSH

Chip select hold time, Output mode

tDCH–20

tOCSL

Chip select pulse width, Output mode

8tDCY

tOCSO

Chip select off time, Output mode

2500

tODD

Output data turn on delay

tODH

Output data hold time

tODOF

Output data turn off delay

tODC

Output data valid

tRST

Reset pulse width

µs

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