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LE58QL022BVC Datasheet(PDF) 21 Page - Zarlink Semiconductor Inc

Part # LE58QL022BVC
Description  Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series
PDF  61 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

LE58QL022BVC Datasheet(HTML) 21 Page - Zarlink Semiconductor Inc

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Le58QL022
Data Sheet
21
Zarlink Semiconductor Inc.
Master Clock
(See Figure 15 for the Master Clock timing diagram.)
Auxiliary Output Clocks
Notes:
1.
If CFAIL = 1 (Command 55h), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or
switching them to default coefficients; otherwise, a chip select off time of 25 µs is required.
2.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3.
The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192
MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128
kHz in Companded state and 256 kHz in Linear state, PCM Signaling state, or double PCLK state. The minimum PCM clock rates should
be doubled for parts with only one PCM highway in order to allow simultaneous access to all four channels.
4.
TSC is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock-slot register.
5.
tTSO is defined as the time at which the output achieves the Open Circuit state.
6.
PCLK and MCLK are required to be integer multiples of the frame sync (FS) frequency. Frame sync is expected to be an accurate 8 kHz
pulse train. If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
7.
Phase jumps of 81 nS will be present when the master clock frequency is a multiple of 1.544 MHz.
No.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
37
JMCY
Master clock jitter
50
ns
6
38
tMCR
Rise time of clock
15
39
tMCF
Fall time of clock
15
40
tMCH
MCLK HIGH pulse width
48
41
tMCL
MCLK LOW pulse width
48
No.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
42
fCHP
Chopper clock frequencyCHP = 0
CHP = 1
256
292.57
kHz
7
42A
DCCHP
Chopper click duty cycle
50
%
7
43
fE1
E1 output frequency (CMODE = EE1 = 1)
4.923
kHz
7
44
tE1
E1 pulse width (CMODE = EE1 = 1)
31.25
µs
7



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