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LE58QL022BVC Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part # LE58QL022BVC
Description  Quad Low Voltage Subscriber Line Audio-Processing Circuit VE580 Series
PDF  61 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

LE58QL022BVC Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

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NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and
technology of Legerity Holdings.
Document ID# 080814
Date:
April 09 2009
Version:
5
Distribution:
Public Document
Le58QL022
Quad Low Voltage Subscriber Line Audio-Processing Circuit
VE580 Series
APPLICATIONS
Codec function on telephone switch line cards
FEATURES
Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
Software and coefficient compatible to the Am79Q02/
021/031 QSLAC device
Performs the functions of four codec/filters
Software programmable:
— SLIC input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock edge
options
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or
8.192 MHz master clock derived from MCLK or PCLK
Built-in test modes with loopback, tone generation,
and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Real Time Data register with interrupt (open drain or
TTL output)
Supports multiplexed SLIC device outputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
Maximum channel bandwidth for V.90 modems
ORDERING INFORMATION
1.
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
2.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Device
Package (Green)1
Packing2
Le58QL022BVC
44-pin TQFP
Tray
RELATED LITERATURE
080754 Le58QL061/063 QLSLAC™ Data Sheet
080147 Le79Q02/021/031 QSLAC™ Data Sheet
080193 Le79Q061/063 QSLAC™ Data Sheet
080761 QSLAC™ to QLSLAC™ Design Conversion
Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
DESCRIPTION
The Le58QL022 Quad Low Voltage Subscriber Line Audio-
Processing Circuit (QLSLAC™) devices integrate the key
functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
Advanced submicron CMOS te chno logy makes the
Le58QL022 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
Signal Processing
Channel 1 (CH 1)
Signal Processing
Channel 2 (CH 2)
Signal Processing
Channel 3 (CH 3)
Signal Processing
Channel 4 (CH 4)
VIN
1
VOUT
1
VIN
2
VOUT
2
VIN
3
VOUT
3
VIN
4
VOUT
4
Analog
SLIC
Clock
&
Reference
Circuits
SLIC
Interface
(SLI)
VREF
CD1
1
CD2
1
C3
1
C4
1
C5
1
CD1
2
CD2
2
C3
2
C4
2
C5
2
CD1
3
CD2
3
C3
3
C4
3
C5
3
CD1
4
CD2
4
C3
4
C4
4
C5
4
Time Slot Assigner
(TSA)
DXA
DRA
TSCA
DXB
DRB
TSCB
Microprocessor Interface
(MPI)
INT
CS
DIO
DCLK
RST
FS
PCLK
MCLK/E1
Dual/Single
PCM
Highway
Microprocessor
CHCLK


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