LE58QL022BVC datasheet(33/61 Pages) ZARLINK

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Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

The low-pass filter band limits the signal. The R filter is composed of a six-tap FIR section operating at a 16 kHz sampling rate and

a one-tap IIR section operating at 8 kHz. It is part of the frequency response correction network. The Analog Impedance Scaling

Network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different SLIC input

impedances from a single external SLIC impedance. The Z filter provides feedback from the transmit signal path to the receive

path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior to

D/A conversion.

Receive PCM Interface

The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to the A-law/µ-law

expansion logic for compressed signals, and then passes the data to the receive path of the signal processor. If the data received

from the PCM highway is programmed for linear code, the A-law/µ-law expansion logic is bypassed and the data is presented to

the receive path of the signal processor directly. The linear data requires two consecutive time slots, while the A-law or

µ-law data

requires a single time slot.

The frame sync (FS) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to it. The logic

contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and

allows up to 128 8-bit c hannels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock

frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system.

The Clock Slot register is 3 bits wide and can be programmed to offset the time slot assignment by 0 to 7 PCLK periods to

eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a

nonzero remainder (R), and when the receive clock slot is greater than R. In that case, the last full receive time slot in the frame

is not usable. If the PCLK frequency is 1.544 MHz (R=1), the receive clock slot can be only 0 or 1 if the last time slot is to be

used. The PCM data can be programmed for input from the DRA or DRB port.

Analog Impedance Scaling Network (AISN)

The AISN is in the QLSLAC device to scale the value of the external SLIC impedance. Scaling this external impedance with the

AISN (along with the Z filter) allows matching of many different line conditions using a single impedance value. Line cards can

meet many different specifications without any hardware changes.

The AISN is a programmable transfer function connected from VIN to VOUT of each QLSLAC device channel. The AISN transfer

function can be used to alter the input impedance of the SLIC device to a new value (ZIN) given by:

where G440 is the SLIC echo gain into an open circuit, G44 is the SLIC echo gain into a short circuit, and ZSL is the SLIC input

impedance without the QLSLAC device.

The gain can be varied from

−0.9375 • GIN to +0.9375 • GIN in 31 steps of 0.0625 • GIN. The AISN gain is determined by the

following equation:

where each AISNi = 0 or 1

There are two special cases to the formula for hAISN: 1) a value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value

of AISN = 10000 is a special case where the AISN circuitry is disabled and VOUT is connected internally to VIN after the input

attenuator with a gain of 0 dB. This allows a Full Digital Loopback state where an input digital PCM signal is completely processed

through the receive section, looped back, processed through the transmit section, and output as digital PCM data. During this

test, the VIN input is ignored and the VOUT output is connected to VREF.

Speech Coding

The A/D and D/A conversion follows either the A-law or the µ-law standard as defined in ITU-T Recommendation G.711. A-law

or µ-law operation is programmed using MPI Command 60/61h. Alternate bit inversion is performed as part of the A-law coding.

The QLSLAC device provides linear code as an option on both the transmit and receive sides of the device. Linear code is

selected using MPI Command 60/61h. Two successive time slots are required for linear code operation. The linear code is a 16-

bit two’s-complement number which appears sign bit first on the PCM highway. Linear code occupies two time slots.

•

AISN

–

() ⁄ 1G

440 • hAISN

–

()

•

AISN

0.0625

GIN

•

AISN

•

∑

⎝⎠

⎜⎟

⎛⎞

–

LE58QL022BVC Datasheet(PDF) 33 Page - Zarlink Semiconductor Inc

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