LE58QL022BVC datasheet(38/61 Pages) ZARLINK

38 / 61 page

Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

QLSLAC devices and the individual CS lines will select the appropriate device to access. Between command sequences, DCLK

can stay in the High state indefinitely with no loss of internal control information regardless of any transitions on the CS lines.

Between bytes of a multibyte read or write command sequence, DCLK can also stay in the High state indefinitely. DCLK can stay

in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a High level.

If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive transitions, only

the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the part occurs. If the chip is in the

middle of a read sequence when CS goes Low, data will be present at the DIO pin even if DCLK has no activity.

SUMMARY OF MPI COMMANDS

Note:

*All codes not listed are reserved by Legerity and should not be used.

MPI COMMAND STRUCTURE

This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow.

For details of the filter coefficients of the form Cxymxy, refer to the General Description of CSD Coefficients section page 54.

Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.

*Default field values are marked by an asterisk. A hardware reset forces the default values.

Hex*

Description

00h

Deactivate (Standby state)

02h

Software Reset

04h

Hardware Reset

06h

No Operation

0Eh

Activate (Operational state)

40/41h

Write/Read Transmit Time Slot and PCM Highway Selection

42/43h

Write/Read Receive Time Slot and PCM Highway Selection

44/45h

Write/Read REC & TX Clock Slot and TX Edge

46/47h

Write/Read Configuration Register

4A/4Bh

Write/Read Channel Enable & Operating Mode Register

4Dh

Read Real Time Data Register

4Fh

Read Real Time Data Register and Clear Interrupt

50/51h

Write/Read AISN and Analog Gains

52/53h

Write/Read SLIC Input/Output Register

54/55h

Write/Read SLIC Input/Output Direction and Status Bits

60/61h

Write/Read Operating Functions

6C/6Dh

Write/Read Interrupt Mask Register

70/71h

Write/Read Operating Conditions

73h

Read Revision Code Number (RCN)

80/81h

Write/Read GX Filter Coefficients

82/83h

Write/Read GR Filter Coefficients

84/85h

Write/Read Z Filter Coefficients (FIR and IIR)

86/87h

Write/Read B1 Filter Coefficients (FIR)

88/89h

Write/Read X Filter Coefficients

8A/8Bh

Write/Read R Filter Coefficients

96/97h

Write/Read B2 Filter Coefficients (IIR)

98/99h

Write/Read Z Filter Coefficients (FIR only)

9A/9Bh

Write/Read Z Filter Coefficients (IIR only)

C8/C9h

Write/Read Debounce Time Register

CDh

Read Transmit PCM Data

E8/E9h

Write/Read Ground Key Filter Sampling Interval

LE58QL022BVC Datasheet(PDF) 38 Page - Zarlink Semiconductor Inc

LE58QL022BVC Datasheet(HTML) 38 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL