LE58QL022BVC datasheet(30/61 Pages) ZARLINK

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Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

the register bits when the interrupt is cleared, a new interrupt is immediately generated with the new data latched into the Real

Time Data register. For this reason, the interrupt logic in the controller should be level-sensitive rather than edge-sensitive.

Interrupt Mask Register

The Real Time Data register data bits can be masked from causing an interrupt to the processor using the interrupt mask register.

The mask register can be written or read via the MPI Command 6C/6Dh.

Active State

Each channel of the QLSLAC device can operate in either the Active (Operational) or Inactive (Standby) state. In the Active state,

individual channels of the QLSLAC device can transmit and receive PCM or linear data and analog information. The Active state

is required when a telephone call is in progress. The activate command (MPI Command 0Eh), puts the selected channel(s) into

this state (see channel enable register). Bringing a channel of the QLSLAC device into the Active state is only possible through

the MPI.

Inactive State

All channels of the QLSLAC device are forced into the Inactive (Standby) state by a power-up or hardware reset. Individual

channels can be programmed into this state by the deactivate command (Command 00h) or by the software reset command

(Command 02h). Power is disconnected from all nonessential circuitry while the MPI remains active to receive commands. The

analog output is tied to VREF through a resistor whose value depends on the VMODE bit. All circuits that contain programmed

information retain their data in the Inactive state.

Chopper Clock

On the Le58QL02JC there is a chopper clock output to drive the switching regulator on some Legerity SLICs. The clock frequency

is selectable as 256 or 292.57 kHz by the CHP bit (Command 46/47h). The duty cycle is given in Switching Characteristics, on

page 19. The chopper output must be turned on with the ECH bit (Command C8/C9h).

Reset States

The QLSLAC device can be reset by application of power, by an active Low on the hardware Reset pin (RST), by a hardware

reset command, or by CS Low for 16 or more rising edges of DCLK. This resets the QLSLAC device to the following state:

A-law companding is selected.

Default B, X, R, and Z filter values from ROM are selected and the AISN is set to zero.

Default digital gain blocks (GX, GR) from ROM are selected. The analog gains, AX and AR, are set to 0 dB and the input

attenuator is turned off (DGIN = 1).

The previously programmed B, Z, X, R, GX, and GR filters in RAM are unchanged.

SLIC I/Os (CD1–C5) are set to the Input state.

All of the test states in the Operating Conditions register are turned off (0’s).

All four channels are in the Inactive (standby) state.

Transmit time slots and receive time slots are set to 0, 1, 2, and 3 for channels 1, 2, 3, and 4, respectively. The clock slots

are set to 0, with transmit on the negative edge.

DXA port is selected for all channels.

10. DRA port is selected for all channels.

11. The master clock frequency selected is 8.192 MHz and is programmed to come from PCLK.

12. All four channels are selected in the Channel Enable register.

13. Any pending interrupts are cleared, all interrupts are masked, and the Interrupt Output state is set to open drain.

14. The supervision debounce time is set to 8 ms.

15. The chopper clock frequency is set to 256 kHz but the chopper clock is turned off.

16. The E1 Multiplex state is turned off (E1 is Hi-Z), and the polarity is set for high going pulses.

17. No signalling on the PCM highway.

LE58QL022BVC Datasheet(PDF) 30 Page - Zarlink Semiconductor Inc

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