LE58QL022BVC datasheet(44/61 Pages) ZARLINK

44 / 61 page

Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

CSTAT = 0

Channel is inactive (Standby state).

CSTAT = 1

Channel is active.

Clock Fail (Read status only, write as 0)

CFAIL* = 0

The internal clock is synchronized to frame synch.

CFAIL = 1

The internal clock is not synchronized to frame synch.

* The CFAIL bit is independent of the Channel Enable Register.

I/O Direction (Read/Write)

IOD5 = 0*

C5 is an input

IOD5 = 1

C5 is an output

IOD4 = 0*

C4 is an input

IOD4 = 1

C4 is an output

IOD3 = 0*

C3 is an input

IOD3 = 1

C3 is an output

IOD2 = 0*

CD2 is an input

IOD2 = 1

CD2 is an output

IOD1 = 0*

CD1 is an input

IOD1 = 1

CD1 is an output

Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3–C5 are not available on the

Le58QL032 QLSLAC device, and C5 is available only on the Le58QL022 QLSLAC device.

* Power Up and Hardware Reset (RST) Value = 00h

60/61h Write/Read Operating Functions

R/W = 0: Write

R/W = 1: Read

Linear Code

C/L = 0*

Compressed coding

C/L = 1

Linear coding

A-law or µ-law

A/µ = 0*

A-law coding

A/µ = 1

µ-law coding

GR Filter

EGR = 0*

Default GR filter enabled

EGR = 1

Programmed GR filter enabled

GX Filter

EGX = 0*

Default GX filter enabled

EGX = 1

Programmed GX filter enabled

X Filter

EX = 0*

Default X filter enabled

EX = 1

Programmed X filter enabled

R Filter

ER = 0*

Default R filter enabled

ER = 1

Programmed R filter enabled

Z Filter

EZ = 0*

Default Z filter enabled

EZ = 1

Programmed Z filter enabled

B Filter

EB = 0*

Default B filter enabled

EB = 1

Programmed B filter enabled

* Power Up and Hardware Reset (RST) Value = 00h.

Command

110000

R/W

I/O Data

C/L

A/µ

EGR

EGX

LE58QL022BVC Datasheet(PDF) 44 Page - Zarlink Semiconductor Inc

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