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LSM6DSV320X Datasheet(PDF) 142 Page - STMicroelectronics |
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LSM6DSV320X Datasheet(HTML) 142 Page - STMicroelectronics |
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142 / 212 page ![]() 13.26 SFLP_QUATZ_L (30h) and SFLP_QUATZ_H (31h) SFLP game rotation vector Z value output register (R). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 327. SFLP_QUATZ_H and SFLP_QUATZ_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 328. SFLP_QUATZ_H and SFLP_QUATZ_L register description D[15:0] SFLP game rotation vector Z value output value 13.27 SFLP_GBIASX_INIT_L (32h) and SFLP_GBIASX_INIT_H (33h) SFLP gyroscope bias X-axis initialization register (R/W). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 329. SFLP_GBIASX_INIT_H and SFLP_GBIASX_INIT_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 330. SFLP_GBIASX_INIT_H and SFLP_GBIASX_INIT_L register description D[15:0] SFLP gyroscope bias X-axis initial value 13.28 SFLP_GBIASY_INIT_L (34h) and SFLP_GBIASY_INIT_H (35h) SFLP gyroscope bias Y-axis initialization register (R/W). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 331. SFLP_GBIASY_INIT_H and SFLP_GBIASY_INIT_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 332. SFLP_GBIASY_INIT_H and SFLP_GBIASY_INIT_L register description D[15:0] SFLP gyroscope bias Y-axis initial value LSM6DSV320X Embedded functions register description DS14623 - Rev 1 page 142/212 |
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