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R7FA2L1AB2DFM Datasheet(PDF) 30 Page - Renesas Technology Corp |
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R7FA2L1AB2DFM Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 114 page ![]() Table 2.11 Operating and standby current (1) (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol LDO mode DCDC mode*12 Unit Test Conditions Typ*10 Max Typ*10 Max Supply current*1 Low- speed mode*3 Normal mode All peripheral clocks disabled, CoreMark code executing from flash*5 ICLK = 2 MHz ICC 0.33 — — — mA *7 All peripheral clocks enabled, code executing from flash*5 ICLK = 2 MHz — 3.1 — — *8 Sleep mode All peripheral clocks disabled*5 ICLK = 2 MHz 0.13 — — — *7 All peripheral clocks enabled*5 ICLK = 2 MHz 0.35 — — — *8 Subosc- speed mode*4 Normal mode All peripheral clocks enabled, code executing from flash*5 ICLK = 32.768 kHz ICC — 540 — — µA *8 Sleep mode All peripheral clocks disabled*5 ICLK = 32.768 kHz 2.00 — — — *8 All peripheral clocks enabled*5 ICLK = 32.768 kHz 5.85 — — — *8 Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. In LDO mode, the supply current is total current flowing into VCC. In DCDC mode, the supply current is total current flowing into VCC and VCC_DCDC. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO and A/D operation. Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution. Note 7. PCLKB and PCLKD are set to divided by 64. Note 8. PCLKB and PCLKD are the same frequency as that of ICLK. Note 9. PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK. Note 10. VCC = 3.3 V. Note 11. The prefetch is operating. Note 12. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V RA2L1 Datasheet 2. Electrical Characteristics R01DS0385EJ0160 Rev.1.60 Oct 14, 2025 Page 30 of 114 |
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