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R7FA2L1AB2DFM Datasheet(PDF) 80 Page - Renesas Technology Corp |
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R7FA2L1AB2DFM Datasheet(HTML) 80 Page - Renesas Technology Corp |
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80 / 114 page  Table 2.60 Data flash characteristics (4) Low-speed operating mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol ICLK = 1 MHz ICLK = 2 MHz Unit Min Typ Max Min Typ Max Programming time 1-byte tDP1 — 86 732 — 57 502 µs Erasure time 1-KB tDE1K — 19.7 504 — 12.4 354 ms Blank check time 1-byte tDBC1 — — 46.5 — — 23.3 µs 1-KB tDBC1K — — 7.3 — — 3.66 ms Suspended time during erasing tDSED — — 22.3 — — 16.2 µs Data flash STOP recovery time tDSTOP 250 — — 250 — — ns Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 2 MHz, the frequency can be set to 1 MHz or 2 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. 2.11.3 Serial Wire Debug (SWD) Table 2.61 SWD characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 — — ns Figure 2.49 SWCLK clock high pulse width tSWCKH 35 — — ns SWCLK clock low pulse width tSWCKL 35 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 16 — — ns Figure 2.50 SWDIO hold time tSWDH 16 — — ns SWDIO data delay time tSWDD 2 — 70 ns Table 2.62 SWD characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 — — ns Figure 2.49 SWCLK clock high pulse width tSWCKH 120 — — ns SWCLK clock low pulse width tSWCKL 120 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 50 — — ns Figure 2.50 SWDIO hold time tSWDH 50 — — ns SWDIO data delay time tSWDD 2 — 170 ns RA2L1 Datasheet 2. Electrical Characteristics R01DS0385EJ0160 Rev.1.60 Oct 14, 2025 Page 80 of 114 |
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