R7FA2L1AB2DFM datasheet(36/114 Pages) RENESAS

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LOCO clock oscillator output

LOCOCR.LCSTP

tLOCO

Figure 2.4

LOCO clock oscillation start timing

HOCO clock

HOCOCR.HCSTP

tHOCOx*1

Note:

x = 24, 32, 48, 64

Figure 2.5

HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)

Sub-clock oscillator output

SOSCCR.SOSTP

tSUBOSC

Figure 2.6

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.22

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

—

Figure 2.7

Not at power-on

tRESW

—

µs

Figure 2.8

Wait time after RES cancellation (at

power-on)

LVD0 enabled*1

tRESWT

—

0.9

—

Figure 2.7

LVD0 disabled*2

—

0.2

—

Wait time after RES cancellation (during

powered-on state)

LVD0 enabled*1

tRESWT2

—

0.9

—

Figure 2.8

LVD0 disabled*2

—

0.2

—

Wait time after internal reset

cancellation (Watchdog timer reset,

SRAM parity error reset, SRAM ECC

error reset, bus master MPU error

reset, bus slave MPU error reset, stack

pointer error reset, software reset)

LVD0 enabled*1

tRESWT3

—

0.9

—

Figure 2.9

LVD0 disabled*2

—

0.15

—

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0160 Rev.1.60

Oct 14, 2025

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