R7FA2L1AB2DFM datasheet(95/114 Pages) RENESAS

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Table A3.2

Access cycles for non-GPT modules

Peripherals

Address

Number of access cycles

ICLK = PCLK

ICLK > PCLK*1

Cycle

unit

Related function

From

Read

Write

Read

Write

MPU, SRAM, BUS,

DTC, ICU, DBG

0x4000_2000

0x4001_BFFF

ICLK

Memory Protection Unit, SRAM,

Buses, Data Transfer Controller,

Interrupt Controller, CPU, Flash

Memory

SYSC

0x4001_E000 0x4001_E6FF

ICLK

Low Power Modes, Resets,

Low Voltage Detection, Clock

Generation Circuit, Register

Write Protection

PORTn, PFS, ELC,

POEG, RTC, WDT,

IWDT, CAC, MSTP

0x4004_0000

0x4004_7FFF

2 to 3

PCLKB

I/O Ports, Event Link Controller,

Port Output Enable for GPT,

Realtime Clock, Watchdog Timer,

Independent Watchdog Timer,

Clock Frequency Accuracy

Measurement Circuit, Module

Stop Control

CAN0,IICn (n =

0, 1),IIC0WU, DOC,

ADC12, DAC12

0x4005_0000

0x4005_EFFF

2 to 3

PCLKB

Controller Area Network Module,

I2C Bus Interface, Data

Operation Circuit, 12-bit A/D

Converter, 12-Bit D/A Converter

SCIn (n = 0*2 to 3, 9)

0x4007_0000

0x4007_0EFF

2 to 3

PCLKB

Serial Communications Interface

SPIn (n = 0, 1)*3

0x4007_2000

0x4007_2FFF

2 to 3

PCLKB

Serial Peripheral Interface

CRC

0x4007_4000

0x4007_4FFF

2 to 3

PCLKB

CRC Calculator

GPT32n (n = 0 to 3),

GPT16n (n = 4 to 9),

GPT_OPS

0x4007_8000

0x4007_BFFF

See Table A3.3.

PCLKB

General PWM Timer

KINT, CTSU

0x4008_0000

0x4008_2FFF

2 to 3

PCLKB

Key interrupt Function,

Capacitive Sensing Unit

AGTn

0x4008_4000

0x4008_4FFF

2 to 3

PCLKB

Low Power Asynchronous

General Purpose Timer

ACMPLP

0x4008_5000

0x4008_6FFF

2 to 3

PCLKB

Low-Power Analog Comparator

FLCN

0x407E_C000 0x407E_FFFF

ICLK

Data Flash, Temperature Sensor,

Capacitive Sensing Unit, Flash

Control

Note 1. If the number of PCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum

value is rounded up to the decimal point. For example, 1.5 to 2.5 is 1 to 3.

Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown

in Table A3.2. When accessing an 8-bit register (FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in Table

A3.2.

Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table A3.2. When accessing an 8-bit or 16-bit

Table A3.3 shows register access cycles for GPT modules.

Table A3.3

Access cycles for GPT modules (1 of 2)

Frequency ratio between ICLK

and PCLK

Number of access cycles

Cycle unit

Read

Write

ICLK > PCLKD = PCLKB

5 to 6

3 to 4

PCLKB

ICLK > PCLKD > PCLKB

3 to 4

2 to 3

PCLKB

PCLKD = ICLK = PCLKB

PCLKB

PCLKD = ICLK > PCLKB

2 to 3

1 to 2

PCLKB

PCLKD > ICLK = PCLKB

PCLKB

RA2L1 Datasheet

Appendix 3. I/O Registers

R01DS0385EJ0160 Rev.1.60

Oct 14, 2025

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