R7FA2L1AB2DFM datasheet(71/114 Pages) RENESAS

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Table 2.49

Power-on reset circuit and voltage detection circuit characteristics (1) (2 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Voltage detection

level*1

Voltage detection

circuit (LVD1)*3

When power supply rise

Vdet1_8

2.63

2.75

2.85

Figure 2.45

At falling edge

VCC

When power supply fall

2.58

2.68

2.78

When power supply rise

Vdet1_9

2.54

2.64

2.75

When power supply fall

2.48

2.58

2.68

When power supply rise

Vdet1_A

2.43

2.53

2.63

When power supply fall

2.38

2.48

2.58

When power supply rise

Vdet1_B

2.16

2.26

2.36

When power supply fall

2.10

2.20

2.30

When power supply rise

Vdet1_C

1.88

2.09

When power supply fall

1.84

1.96

2.05

When power supply rise

Vdet1_D

1.78

1.9

1.99

When power supply fall

1.74

1.86

1.95

When power supply rise

Vdet1_E

1.67

1.79

1.88

When power supply fall

1.63

1.75

1.84

When power supply rise

Vdet1_F

1.65

1.7

1.78

When power supply fall

1.60

1.65

1.73

Voltage detection

level*1

Voltage detection

circuit (LVD2)*4

When power supply rise

Vdet2_0

4.20

4.40

4.57

Figure 2.46

At falling edge

VCC

When power supply fall

4.11

4.31

4.48

When power supply rise

Vdet2_1

4.05

4.25

4.42

When power supply fall

3.97

4.17

4.34

When power supply rise

Vdet2_2

3.91

4.11

4.28

When power supply fall

3.83

4.03

4.20

When power supply rise

Vdet2_3

3.71

3.91

4.08

When power supply fall

3.64

3.84

4.01

Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection

level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection.

Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL0[2:0] bits.

Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.

Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

Table 2.50

Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Wait time after power-on

reset cancellation

LVD0: enable

tPOR

—

4.3

—

LVD0: disable

tPOR

—

3.7

—

Wait time after voltage

monitor 0, 1, 2 reset

cancellation

LVD0: enable*1

tLVD0,1,2

—

1.4

—

LVD0: disable*2

tLVD1,2

—

0.7

—

Power-on reset response delay time*3

tdet

—

500

µs

Figure 2.42, Figure 2.43

LVD0 response delay time*3

tdet

—

500

µs

Figure 2.44

LVD1 response delay time*3

tdet

—

350

µs

Figure 2.45

LVD2 response delay time*3

tdet

—

600

µs

Figure 2.46

Minimum VCC down time

tVOFF

500

—

µs

Figure 2.42, VCC = 1.0 V or

above

Power-on reset enable time

tW (POR)

—

Figure 2.43, VCC = below 1.0

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0160 Rev.1.60

Oct 14, 2025

Page 71 of 114

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